Publications

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Conference Publications

X. Fong, M.-C. Chen, and K. Roy, “Generating true random numbers using on-chip complementary polarizer spin-transfer torque magnetic tunnel junctions,” in Proc. of 72^nd Device Research Conf. (DRC), Jun. 2014, pp. 103-104, doi:10.1109/DRC.2014.6872318 [PDF]
X. Fong, and K. Roy, “A hybrid spin-charge mixed-mode simulation framework for evaluating STT-MRAM bit-cells utilizing multiferroic tunnel junctions,” in Proc. of 2013 Int. Conf. on Simulation of Semicond. Processes and Dev. (SISPAD), Sep. 2013, pp. 372-375, doi:10.1109/SISPAD.2013.6650652 [PDF]
X. Fong, and K. Roy, “Robust low-power multi-terminal STT-MRAM,” in Proc. of 13^th Non-volatile Memory Technology Symposium (NVMTS), Aug. 2013, pp. 1-4, doi:10.1109/NVMTS.2013.6851056 [PDF]
X. Fong, and K. Roy, “Low-power robust complementary polarizer STTMRAM (CPSTT) for on-chip caches,” in Proc. of 5^th Int. Memory Workshop (IMW 2013), May 2013, pp. 88-91, doi:10.1109/IMW.2013.6582105 [PDF]
- Errata
  1. Parameters in Table I should be: $V_{DD}~=~1.4\text{V}$
  2. Table II should have same values for CPSTT and SSCs: $I_{C}~=~210{\mu}\text{A},~J_{C}~=~8.4\text{MA/cm}^{2}_{}$
X. Fong, S. K. Gupta, N. N. Mojumder, S. H. Choday, C. Augustine, and K. Roy, “KNACK: a hybrid spin-charge mixed-mode simulator for evaluating different genres of spin-transfer torque MRAM bit-cells,” in Proc. of 2011 Int. Conf. on Simulation of Semicond. Processes and Dev. (SISPAD), Sep. 2011, pp. 51-54, doi:10.1109/SISPAD.2011.6035047 [PDF]
- Errata
  1. Equation (4) should be: $\frac{\partial\widehat{m}}{\partial t}=-\left|{\gamma_{}^{}}\right|\widehat{m}\times\left(\overrightarrow{H}_\text{EFF}+\overrightarrow{STT}\right)+{\alpha}\widehat{m}\times\frac{\partial\widehat{m}}{\partial t}$
  2. Equation (11) should be: $\overrightarrow{STT}_{}^{}=\frac{{\hbar}g\left(\widehat{m}\cdot\widehat{m}_{p}\right)J_{MTJ}}{2q{\mu}_{0}M_{S}t_{FL}}\left(\widehat{m}\times\widehat{m}_{p}\right)+\epsilon'\frac{{\hbar}J_{MTJ}}{2q\mu_{0}M_{S}t_{FL}}\widehat{m}_{p}$
Z. Pajouhi, X. Fong, and K. Roy, “Device/Circuit/Architecture co-design of reliable STT-MRAM,” in Proc. of IEEE/ACM Design, Automation &Test in Europe (DATE), Mar. 2015, pp. 1437-1442, [PDF]
L. Zhang, X. Fong, C. H. Chang, Z. H. Kong, and K. Roy, “Highly reliable memory-based physical unclonable function using spin-transfer torque MRAM,” in Proc. of 2014 IEEE Int. Symp. on Circuits and Systems, Jun. 2014, pp. 2169-2172, doi:10.1109/ISCAS.2014.6865598 [PDF]
L. Zhang, X. Fong, C. H. Chang, Z. H. Kong, and K. Roy, “Feasibility study of emerging non-volatile memory based physical unclonable functions,” in Proc. of 6^th Int. Memory Workshop, May 2014, pp. 1-4, doi:10.1109/IMW.2014.6849384 [PDF]
M. Sharad, X. Fong, and K. Roy, “Exploring the design of ultra-low energy global interconnects based on spin torque switches,” in Proc. of IEEE Int. Electron Device Meeting (IEDM) 2013, Dec. 2013, pp. 32.6.1-32.6.4, doi:10.1109/IEDM.2013.6724739 [PDF]
C. Augustine, X. Fong, and K. Roy, “Dual ferroelectric capacitor architecture and its application to TAG RAM,” in Proc. of IEEE Int. Conf. on Integrated Circuit Design Technology (ICICDT) 2010, Jun. 2010, pp. 24-38, doi:10.1109/ICICDT.2010.5510750 [PDF]
C. Augustine, X. Fong, B. Behin-Aein, and K. Roy, “A comprehensive nano-magnet based logic synthesis for ultra-low power digital systems,” SRC TECHCON 2009 (Best Paper in Session Award)
A. Raychowdhury, X. Fong, Q. Chen, and K. Roy, “Analysis of super cut-off transistors for ultralow power digital logic circuits,” in Proc. of 2006 Int. Symposium on Low Power Electronics and Design (ISLPED), Oct. 2006, pp. 2-7, doi:10.1109/LPE.2006.4271798 (Best Paper Award) [PDF]
G. Narasimman, S. Roy, X. Fong, K. Roy, C.-H. Chang, and A. Basu, “A Low-voltage, Low Power STDP Synapse Implementation using Domain-wall Magnets for Spiking Neural Networks,” in Proc. of 2016 IEEE Int. Symposium on Circuits and Systems (ISCAS), May 2016, pp. 914-917, doi:10.1109/ISCAS.2016.7527390 (Invited Paper) [PDF]
K. Yogendra, M.-C. Chen, X. Fong, and K. Roy, “Domain wall motion based low power hybrid spin-CMOS 5-bit Flash analog data converter,” in Proc. of 16th IEEE Int. Symposium on Quality Electronic Design (ISQED), Mar. 2015, pp. 604-609, doi:10.1109/ISQED.2015.7085496 [PDF]
A. Ranjan, S. Venkataramani, X. Fong, K. Roy, and A. Raghunathan, “Approximate storage for energy efficient spintronic memories,” in Proc. of IEEE/ACM Design, Automation & Test in Europe (DATE), Mar. 2015, pp. 1-6, doi:10.1145/2744769.2744799 [PDF]
R. Venkatesan, S. Venkataramani, X. Fong, K. Roy, and A. Raghunathan, “Spintastic: Spin-based stochastic logic for energy-efficient computing,” in Proc. of IEEE/ACM Design, Automation & Test in Europe (DATE), Mar. 2015, pp. 1575-1578, [PDF]
M. Sharad, R. Venkatesan, X. Fong, A. Raghunathan, and K. Roy, “Energy-efficient MRAM access scheme using hybrid circuits based on spin-torque sensors,” in Proc. of 2013 IEEE Sensors, Nov. 2013, pp. 2-7, doi:10.1109/ICSENS.2013.6688182 [PDF]
M. Sharad, R. Venkatesan, X. Fong, A. Raghunathan, and K. Roy, “Reading spin-torque memory with spin-torque sensors,” in Proc. of 2013 IEEE/ACM Int. Symp. on Nanoscale Architectures (NANOARCH), Jul. 2013, pp. 40-41, doi:10.1109/NanoArch.2013.6623040 [PDF]
G. Panagopoulos, C. Augustine, X. Fong, and K. Roy, “Exploring variability and reliability of multi-level STT-MRAM cells,” in Proc. 70^th Device Research Conference (DRC), Jun. 2012, pp. 139-140, doi:10.1109/DRC.2012.6257003 [PDF]
C. Augustine, N. N. Mojumder, X. Fong, S. H. Choday, S. P. Park, and K. Roy, “STT-MRAMs for future universal memories: Perspective and prospective,” in Proc. 28^th Int. Conf. on Microelectronics (MIEL), May 2012, pp. 349-355, doi:10.1109/MIEL.2012.6222872 [PDF]
C. Augustine, B. Behin-Aein, X. Fong, and K. Roy, “A design methodology and device/circuit/architecture compatible simulation framework for low-power magnetic quantum cellular automata systems,” in Proc. of 14^th Asia and South Pacific Design Automation Conf. (ASP-DAC) 2009, Jan. 2009, pp. 847-852, doi:10.1109/ASPDAC.2009.4796586 [PDF]

Journal Publications

X. Fong, Y. Kim, R. Venkatesan, S. H. Choday, A. Raghunathan, and K. Roy, “Spin-transfer Torque Memories: Devices, Circuits and Systems,” Proceedings of the IEEE vol. 104, iss. 7, pp. 1449-1488, Jul. 2016, doi:10.1109/JPROC.2016.2521712 [PDF]
X. Fong, R. Venkatesan, D. Lee, A. Raghunathan, and K. Roy, “Embedding read-only memory in spin-transfer torque MRAM based on-chip caches,” IEEE Trans. Very Large Scale Integration (TVLSI) Systems vol. 24, no. 3, pp. 992-1002, Mar. 2016, doi:10.1109/TVLSI.2015.2439733 [PDF]
X. Fong, Y. Kim, K. Yogendra, D. Fan, A. Sengupta, A. Raghunathan, and K. Roy, “Spin-transfer torque devices for logic and memory applications: prospects and perspectives,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems vol. 35, iss. 1, pp. 1-22, Jan. 2016, doi:10.1109/TCAD.2015.2481793 Invited Paper. [PDF]
X. Fong, R. Venkatesan, A. Raghunathan, and K. Roy, “Non-volatile complementary polarizer spin-transfer torque (CPSTT) on-chip caches: a device/circuit/systems perspective,” IEEE Trans. Magnetics (TMAG) vol. 50, iss. 10, art. 3400611, Oct. 2014, doi:10.1109/TMAG.2014.2326858 [PDF]
X. Fong, and K. Roy, “Complementary polarizers STT-MRAM (CPSTT) for on-chip caches,” IEEE Electron Device Letters vol. 34, iss. 2, pp. 232-234, Feb. 2013, doi:10.1109/LED.2012.2234079 [PDF]
- Errata
  1. Page 232, Title: “Complimentary” should be replaced with “Complementary”
  2. Page 232, Column 1, Last sentence of Section I: “complimentary polarizers” should be replaced with “complementary polarizers”
  3. Page 233, title in running header: “COMPLIMENTARY” should be replaced with “COMPLEMENTARY”
X. Fong, Y. Kim, S. H. Choday, and K. Roy, “Failure mitigation techniques for 1T-1MTJ spin-transfer torque MRAM bit-cells,” IEEE Trans. Very Large Scale Integration (TVLSI) Systems vol. 22, iss. 2, pp. 384-395, Feb. 2014, doi:10.1109/TVLSI.2013.2239671 [PDF]
- Errata
  1. Units of “Nominal $J_{C}^{}$ ” in Table I should be $\text{``MA/cm}^{2}_{}\text{''}$ instead of $\text{``mA/cm}^{2}_{}\text{''}$
X. Fong, S. H. Choday, and K. Roy, “Bit-cell level optimization for non-volatile memories using magnetic tunnel junctions and spin-transfer torque switching,” IEEE Trans. Nanotechnol. (TNANO) vol. 11, no. 1, pp. 172-181, Jan. 2012, doi:10.1109/TNANO.2011.2169456 [PDF]
A. Jaiswal, X. Fong, and K. Roy, “Comprehensive Scaling Analysis of Current Induced Switching in Magnetic Memories Based on In-Plane and Perpendicular Anisotropies,” IEEE Journal on Emerging and Selected Topics in Circuits and Systems vol. 6, iss. 2, pp. 120-133, Jun. 2016, doi:10.1109/JETCAS.2016.2547698 [PDF]
Y. Kim, X. Fong, and K. Roy, “Spin-orbit torque based spin-dice: a true random number generator,” IEEE Magnetics Letters vol. 6, art. 3001004, Dec. 2015, doi:10.1109/LMAG.2015.2496548 [PDF]
K. Kwon, X. Fong, P. Wijesinghe, P. Panda, and K. Roy, “High-Density & Robust STT-MRAM Array through Device/Circuit/Architecture Interactions,” IEEE Trans. Nanotechnol. (TNANO) vol. 14, iss. 6, pp. 1024-1034, Nov. 2015, doi:10.1109/TNANO.2015.2456510 [PDF]
L. Zhang, X. Fong, C.-H. Chang, Z. H. Kong, and K. Roy, “Optimizing Emerging Non-Volatile Memories for Dual-Mode Applications: Data Storage and Key Generator,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems (TCAD) vol. 34, no. 7, pp. 1176-1187, Jul. 2015, doi:10.1109/TCAD.2015.2427251 [PDF]
L. Zhang, X. Fong, C.-H. Chang, Z. H. Kong, and K. Roy, “Highly Reliable Spin-Transfer Torque Magnetic RAM based Physical Unclonable Function With Multi-Response-Bits Per Cell,” IEEE Trans. on Information Forensics and Security (TIFS) vol. 10, no. 8, pp. 1630-1642, Aug. 2015, doi:10.1109/TIFS.2015.2421481 [PDF]
Y. Seo, X. Fong, K.-W. Kwon and K. Roy, “Spin-Hall Magnetic Random-Access Memory with Dual Read/Write Ports for On-chip Caches,” IEEE Magnetics Letters vol. 6, art. 3000204, Apr. 2015, doi:10.1109/LMAG.2015.2422260 [PDF]
Y. Seo, X. Fong, and K. Roy, “Domain wall coupling based STT-MRAM for on-chip cache applications,” IEEE Trans. on Electron Devices (TED) vol. 62, iss. 2, pp. 554-560, Feb. 2015, doi:10.1109/TED.2014.2377751 [PDF]
Y. Kim, X. Fong, K.-W. Kwon, M.-C. Chen, and K. Roy, “Multi-level spin-orbit torque MRAMs,” IEEE Trans. on Electron Devices (TED) vol. 62, iss. 2, pp. 561-568, Jan. 2015, doi:10.1109/TED.2014.2377721 [PDF]
Z. Al Azim, X. Fong, T. Ostler, R. Chantrell, and K. Roy, “Laser induced magnetization reversal for detection in optical interconnects,” IEEE Electron Device Letters (EDL) vol. 35, iss. 12, pp. 1317-1319, Oct. 2014, doi:10.1109/LED.2014.2364232. [PDF]
D. Lee, X. Fong, and K. Roy, “R-MRAM: A ROM-Embedded STT MRAM Cache,” IEEE Electron Dev. Lett. vol. 34, iss. 10, pp. 1256-1258, Oct. 2013, doi:10.1109/LED.2013.2279137 [PDF]
N. N. Mojumder, X. Fong, C. Augustine, S. K. Gupta, S. H. Choday, and K. Roy, “Dual pillar spin-transfer torque MRAMs for low power applications,” ACM Journal on Emerging Technologies in Computing Systems (JETC) vol. 9, iss. 2, art. 14, May 2013, doi:10.1145/2463585.2463590 [PDF]
C. Augustine, X. Fong, B. Behin-Aein, and K. Roy, “Ultra-low power nano-magnet based computing: a system-level perspective,” IEEE Trans. Nanotechnol. (TNANO) vol. 10, 4, pp. 778-788, Jul. 2010, doi:10.1109/TNANO.2010.2079941 [PDF]
Y. Seo, K.-W. Kwon, X. Fong, and K. Roy, “High Performance and Energy-Efficient On-Chip Cache Using Dual Port (1R/1W) Spin-Orbit Torque MRAM,” to appear in IEEE Journal on Emerging and Selected Topics in Circuits and Systems, doi:10.1109/JETCAS.2016.2547701 [PDF]
A. Reza, Z. Al Azim, X. Fong, and K. Roy, “Modeling and Evaluation of Topological Insulator/Ferromagnet Heterostructure Based Memory,” IEEE Trans. Electron Devices (TED) vol. 63, no. 3, pp. 1359-1367, Mar. 2016, doi:10.1109/TED.2016.2520941 [PDF]
A. Sengupta, Z. Al Azim, X. Fong, and K. Roy, “Spin-orbit torque induced spike-timing dependent plasticity,” Appl. Phys. Lett. (APL), vol. 106, iss. 9, 093704, Mar. 2015, doi:10.1063/1.4914111 [PDF]
K. Roy, D. Fan, X. Fong,Y. Kim, M. Sharad, S. Paul, S. Chatterjee, S. Bhunia, and S. Mukhopadhyay, “Exploring spin transfer torque devices for unconventional computing,” IEEE J. on Emerging and Selected Topics in Circuits and Systems (JETCAS) vol. 5, no. 1, pp. 5-16, Mar. 2015, doi:10.1109/JETCAS.2015.2405171. Invited Paper [PDF]
Y. Seo, K. Kwon, X. Fong, and K. Roy, “High Performance and Energy-Efficient On-Chip Cache using Dual Port (1R/1W) Spin-Orbit Torque MRAM,” accepted for publication in J. Emerging Topics in Cicruits and Systems (JETCAS) [PDF]
C. Augustine, N. Mojumder, X. Fong, H. Choday, S. Park, and K. Roy, “Spin-Transfer Torque MRAMs for Low Power Memories: Perspective and Prospective,” IEEE J. Sensors vol. 12, no. 4, pp. 756-766, Apr. 2012, doi:10.1109/JSEN.2011.2124453. Invited Paper [PDF]
K.-W. Kwon, S. H. Choday, Y. Kim, X. Fong, S. P. Park, and K. Roy, “SHE-NVFF: spin Hall effect based nonvolatile flip flop for power gating architecture,” IEEE Electron Device Letters vol. 35, iss. 4, pp. 488-490, Apr. 2014, doi:10.1109/LED.2014.2304683 [PDF]

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